1. Field of the Invention
This invention relates to a semiconductor device having a ferroelectric film and a manufacturing method thereof and more particularly to a ferroelectric capacitor in a ferroelectric memory (FeRAM).
2. Description of the Related Art
Recently, as semiconductor memories, volatile DRAMs (Dynamic RAMS), SRAMs (Static RAMs), nonvolatile MROMs (Mask ROMs), Flash EEPROMs and ferroelectric memories (FeRAMs) are on the market.
The ferroelectric memory stores binary data in a nonvolatile fashion depending on the magnitude of two different residual dielectric polarizations of a ferroelectric capacitor based on the hysteresis characteristic which is one of the characteristics of a ferroelectric material.
Like in the case of a DRAM, some of the memory cells which configure a conventional ferroelectric memory are each configured by serially connecting a capacitor and a transistor. In such a ferroelectric memory, a ferroelectric capacitor can be formed by performing a photolithography process once. That is, an upper electrode and lower electrode of the ferroelectric capacitor and a ferroelectric film between the upper and lower electrodes can be formed by performing a photolithography process once. The photolithography process indicates a process in which a resist film is formed, a resist pattern is formed by exposure and development and a to-be-coated film under the resist pattern is formed by use of the resist pattern.
Further, some other memory cells which configure another conventional ferroelectric memory have the following configuration.
A series connected TC unit type ferroelectric memory comprises series connected memory cells each having a transistor (T) having a source and a drain and a ferroelectric capacitor (C) inbetween the source and the drain.
FIG. 1A is a plan view of a ferroelectric capacitor in the conventional series connected TC unit type ferroelectric memory and FIG. 1B is a cross sectional view showing the structure of the ferroelectric capacitor.
As shown in FIG. 1B, source and drain diffusion layers 102 are separately formed in the surface region of a semiconductor substrate 101. A gate electrode 104 of each cell transistor is formed over a portion of the semiconductor substrate 101 which lies between the source and drain diffusion layers 102 with a gate insulating film 103 interposed between the portion of the semiconductor substrate 101 and the gate electrode 104.
An interlayer insulating film 105 is formed on the semiconductor substrate 101. A lower electrode 106, a ferroelectric film 107 and upper electrodes 108 which configure the ferroelectric capacitors are formed in this order in the interlayer insulating film 105.
The ferroelectric film 107 is formed on the lower electrode 106. Two separated upper electrodes 108 are formed on the ferroelectric film 107. Further, the lower electrode 106 is connected to a corresponding one of the source and drain diffusion layers 102 and one of the two upper electrode 108 is connected to the other of the source and drain diffusion layers 102.
Thus, the ferroelectric capacitor of the ferroelectric memory has a structure in which one pair of upper electrodes 108 are disposed over one lower electrode 106.
In the series connected TC unit type ferroelectric memory as shown in FIGS. 1A and 1B, since a structure in which one pair of upper electrodes 108 are disposed over one lower electrode 106 is formed as described before, it is necessary to perform the photolithography process at least twice in order to form a capacitor having one lower electrode 106 and one pair of upper electrodes 108.
More specifically, the following process is performed. In the conventional series connected TC unit type ferroelectric memory, upper electrodes 108 are formed by use of a first mask. Then, after a second mask is formed to protect each pair of upper electrodes 108, ferroelectric films 107 and lower electrodes 106 are formed.
In the process using two mask steps, misalignment occurs between the first and second masks. Therefore, as shown in FIG. 1A, it is necessary to provide a margin of a misalignment portion 109 between the upper electrode 108 formed by use of the first mask and the lower electrode 106 formed by use of the second mask. As a result, the cell area of the capacitor is increased by an amount corresponding to the misalignment portion and there occurs a problem that the occupied area on the chip of the ferroelectric memory having the capacitors incorporated therein is increased.
According to an aspect of the present invention, there is provided a semiconductor device comprising a first semiconductor region formed in a surface region of a semiconductor substrate; a second semiconductor region formed separately from the first semiconductor region in a surface region of the semiconductor substrate; a gate insulating film formed on a portion of the semiconductor substrate which lies between the first semiconductor region and the second semiconductor region; a gate electrode formed on the gate insulating film; an interlayer insulating film formed on the semiconductor substrate to cover the first semiconductor region, second semiconductor region and gate electrode; first and second lower electrodes formed on the interlayer insulating film; a first contact plug formed in the interlayer insulating film in contact with the first lower electrode; a second contact plug formed in the interlayer insulating film separately from the first contact plug and in contact with the second lower electrode; a first ferroelectric film formed on the first lower electrode; a first upper electrode formed on the first ferroelectric film; a second ferroelectric film formed on the second lower electrode; and a second upper electrode formed on the second ferroelectric film.
According to another aspect of the present invention, there is provided a semiconductor device manufacturing method comprising forming a gate electrode over a semiconductor substrate with a gate insulating film interposed between the semiconductor substrate and the gate electrode; forming source and drain diffusion layers on a surface of the semiconductor substrate on both sides of the gate electrode; forming a first interlayer insulating film on the semiconductor substrate to cover the gate electrode, source and drain diffusion layers; forming a buried interconnection and a first contact plug which extends from a portion of the buried interconnection to one of the source diffusion layer and the drain diffusion layer in the first interlayer insulating film which lies on the source and drain diffusion layers; forming a second interlayer insulating film on the first interlayer insulating film and on the buried interconnection containing the first contact plug; forming a pair of second and third contact plugs which extend from the surface of the second interlayer insulating film to the buried interconnection in the second interlayer insulating film formed on the buried interconnection; and forming a first ferroelectric capacitor by sequentially laminating a first lower electrode, first ferroelectric film and first upper electrode in this order on the second contact plug and forming a second ferroelectric capacitor by sequentially laminating a second lower electrode, second ferroelectric film and second upper electrode in this order on the third contact plug.